https://www.ee.iitm.ac.in/~nagendra/cadinfo.html
Saturday, August 16, 2025
Thursday, August 14, 2025
If You Want to Add Value to Open EDA - chatGPT's Advice
EDA Automation for Analog — a 90-Day MVP You Can Start Today
Build the missing glue: auto testbenches, corner/MC orchestration, lint, and clean HTML reports — open-source first, portable to Virtuoso/Spectre later.
Strategy in One Paragraph
Tool Stack (Free)
Milestones & Deliverables
Weeks 1–2 v0.1
- Repo layout:
tools/,examples/,reports/,docs/ gen_tb.py— Jinja SPICE TB generatorrun_corners.py— PVT runner (real if ngspice found; mock otherwise)report_html.py— JSON → HTML reportschematic_lint.py— basic xschem lint (stub)
Success: An inverter example renders a shareable HTML report.
Weeks 3–4 v0.2
- YAML-driven corners (VDD, temp, tt/ss/ff when available)
- Parameter sweeps:
cload, W/L, bias current - Measurements:
tpHL/tpLH, tr/tf, static current - Artifacts:
summary.json,results.csv, sortable HTML
Success: 6+ corners with one command, neat table output.
Weeks 5–6 MC
- Monte Carlo with deterministic seeds
- Stats & yield: mean/σ/min/max, pass/fail vs. spec
- HTML distributions + yield bar
Success: 200-run MC of comparator delay across 3 corners.
Weeks 7–8 Lint
- Schematic lint: unlabeled nets, P/G rails, floating nodes, naming consistency
- Layout lint (KLayout): symmetry pairs, matched areas, orientation checks
- Checklist emitted into HTML
Success: Actionable lint before LVS/DRC, fewer late surprises.
Weeks 9–10 LVS/DRC
- Wrap netgen (LVS): device/net mismatches, pin naming
- Wrap Magic/KLayout (DRC): total errors, top rules, coordinates
- One-page sign-off snapshot
Success: PVT + MC + LVS/DRC summary on one screen.
Weeks 11–12 v0.4
- Cell pack: Inverter, Comparator, Two-stage Op-Amp (or simple LDO stage)
- Each with ready configs, corners, MC, lint, LVS/DRC
- One-Click:
run_all.py examples/opamp/config.yaml
Success: A non-expert can clone & run and get a professional report.
Example: Minimal Workflow
# 1) Generate a testbench from YAML
python tools/gen_tb.py examples/inverter/config.yaml
# 2) Run corners (uses ngspice if present; otherwise mock)
python tools/run_corners.py examples/inverter/config.yaml --out reports/inverter
# 3) Build a shareable HTML report
python tools/report_html.py reports/inverter/summary.json --out reports/inverter/report.html
What to Automate (High Value)
- Auto Testbench Generation: from a small YAML “design contract” (pins, supplies, stimulus recipe) → SPICE with measures.
- Corner/MC Orchestration: reproducible seeds, resumable runs, cache, CSV+JSON artifacts, CI-friendly.
- Lint: schematic (nets, names, floating nodes) and layout (symmetry/matching heuristics) for early catches.
- HTML Reports: specs vs targets, pass/fail heatmap, MC yield, LVS/DRC counts, links to artifacts.
Porting to Cadence/Synopsys Later
Design with adapters so swapping tools is trivial:
- Simulator:
NgspiceAdapter⇄SpectreAdapter(CLI args, netlist dialect, measures/Ocean) - Schematic: xschem parse ⇄ Virtuoso via SKILL/Ocean or exported netlists
- Layout Checks: KLayout scripts stay useful even in Virtuoso flows; later swap to Calibre/PVS wrappers
The value isn’t replacing Virtuoso — it’s automating everything around it.
Validation & First “Customers”
- Who first: small analog consultancies & university labs (hate manual PVT/MC + reporting).
- Pilot: offer your stack free to 1–2 teams for feedback and anonymized screenshots.
- Measure: time saved/iteration, bugs caught by lint pre-LVS/DRC, earlier MC yield visibility.
Risks & Mitigations
- Open PDK limits: use Sky130/GF180 to prove flow; keep adapters ready for proprietary PDKs.
- Layout heuristics: start with simple symmetry checks; evolve toward device-graph matching.
- Vendor lock-in: strict adapter boundaries to avoid rewrites when adding Spectre/Calibre.
Quick Start Checklist
- Python 3.11+, optional ngspice on PATH
- YAML config describing pins, supplies, stimulus, corners, MC
- Run: generate TB → run corners/MC → build HTML
- Iterate: add lint and LVS/DRC wrappers, then ship one-click reports
Want an expanded YAML schema, a first KLayout symmetry macro, or a SKILL/Ocean mapping sheet to Virtuoso? Say the word and I’ll include them in a follow-up post.
Who Needs Cadence Anymore (for Schematic Tree Reporting that is :)? Make Your Own Reporter with chatGPT!
You know what I mean, if you've used Cadence - the SHIFT-T thing that gives you the schematic tree can be VERY useful, at times. No Cade...
-
https://www.openedhardware.com/p/an-interview-with-stefan-schippers Xschem LoC : 35k (Source : https://github.com/StefanSchippers/xschem )...
-
https://cboard.cprogramming.com/c-programming/88495-development-process.html Start with a skeleton and build the program up bit by bit, maki...
-
☐ Analyze code formatting and style consistency ☐ Evaluate naming conventions and clarity ☐ Assess function complexity and ...
